Digital signals are frequently encoded at a source location and decoded at a remote location. When the encoded signal is received at the remote decoding site, the decoding clock may operate at a different frequency than did the encoder clock upstream If the decoder is not synchronized with the encoder, processed data may come into the decoder at too high a frequency, or the output from the decoder may not be available when required. To overcome this serial clock synchronization problem, two methods have historically been employed. First, decoder clocks have been designed to perform at the identical rate of the encoder clock. However, over time, either the decoder or encoder clock may drift, causing the decoder not to have enough information or to have too much information when processing the signal. The decoder clock may be behind or ahead of the encoder clock even though both may have been designed to perform identically. Phase lock loops (PLLs) have been employed to control synchronization and drift problems. Phase lock loops are well known within digital circuitry to provide frequency control. The problem with PLLs is that they are difficult to implement in digital ASICs (application specific integrated circuits). Further, audio signals will generally have a ratio of 1000 to 1 between encoder (remote)and decoder (local) clocks. With this ratio, PLLs frequently cause clock jitter, which significantly reduces the performance of digital audio circuits.
Phase lock loops generally are not able to generate a fast enough shift for a digital-to-analog (D/A) converter. PLLs are too slow to make the dynamic frequency changes necessary for audio clock applications, and incorrect frequency response may cause errors in the decoder.
The second method used to solve the problem is to use hardware which detects that the decoder clock is behind or ahead of the encoder clock. The frequency of the oscillating device may then be changed using a voltage controlled crystal oscillator (VCXO). Detection devices, however, are expensive and add greatly to system complexity.
Accordingly, a principle object of the present invention is to provide circuitry which synchronizes serial digital bitstreams transmitted from an encoder to a decoder and provides optimum performance for misaligned decoder and encoder clocks.
A further object of this invention is to provide a low cost, low complexity digital audio clock synchronization circuit which is easy to implement, does not cause jitter or other audio performance degradation, and responds robustly to misaligned clock signals.